simuhw.alu package

Module contents

class simuhw.alu.GenericArithmeticLogicUnit(ops: Iterable[Operator])

Bases: Device

A generic arithmetic logic unit.

This device can integrate any operator devices.

__init__(ops: Iterable[Operator]) → None

Creates a generic arithmetic logic unit.

Parameters:

ops – The operator devices to be integrated.

property ops: tuple[Operator, ...]

The integrated operator devices.

property width_i: int

The bit width of the input ports.

property width_o: int

The bit width of the output port.

property width_op: int

The bit width of the operator device selection port.

property width_s: int

The bit width of the SIMD word width selection port.

property width_ft: int

The bit width of the input port to set tininess detection mode.

The value is 0 unless simuhw.fp submodule is available.

property width_fr: int

The bit width of the input port to set rounding mode.

The value is 0 unless simuhw.fp submodule is available.

property width_fe: int

The bit width of the input and output ports to set and get floating-point exception flags.

The value is 0 unless simuhw.fp submodule is available.

property ports_i: tuple[InputPort, ...]

The input ports.

property port_o: OutputPort

The output port.

property port_op: InputPort

The operator device selection port.

property port_s: InputPort

The SIMD word width selection port.

property port_ci: InputPort

The carry input port.

The width is 1 bit.

property port_co: OutputPort

The carry output port.

The width is 1 bit.

property port_e: OutputPort

The output port to emit overflow exception of integer multiplication and division.

The width is 1 bit.

property port_ft: InputPort

The input port to set the tininess detection mode.

property port_fr: InputPort

The input port to set the rounding mode.

property port_fe_i: InputPort

The input port to set the floating-point exception flags.

property port_fe_o: OutputPort

The output port to get the floating-point exception flags.

reset() → None

Resets the states.

find_op_indices(cond: tuple[type[Operator], int, int]) → list[int]

Returns the indices of the integrated operator devices that match the specified condition.

Each index can be used to create a word for the operator device selection port (port_op).

Parameters:

cond – The condition to be matched with the integrated operator devices. The first tuple element is the type of the operator device, the second tuple element is the bit width of the input port or ports, and the third tuple element is the bit width of the output port.

Returns:

The indices of the integrated operator devices that match the specified condition.

work(time: float | None) → tuple[list[InputPort], float | None]

Makes the device work.

Parameters:

time – The current time in seconds. None when starting to make the device work.

Returns:

A tuple of the list of the input ports that are to be watched receive a signal, and the next resuming time in seconds. The next resuming time can be None if resumable anytime.

class simuhw.alu.FullArithmeticLogicUnit(dsize: int | Iterable[int], *, use_int: bool = True, use_fp: bool = False, use_fp_riscv: bool = False, add_ops: Iterable[Operator] = [])

Bases: GenericArithmeticLogicUnit

A full arithmetic logic unit.

This device integrates all operator devices supported by SimuHW.

__init__(dsize: int | Iterable[int], *, use_int: bool = True, use_fp: bool = False, use_fp_riscv: bool = False, add_ops: Iterable[Operator] = []) → None

Creates a full arithmetic logic unit.

Parameters:

• dsize – The word width or widths in bits.

• use_int – If it is True, all integer operator devices other than architecture-specific ones are integrated. Every multiple-input bitwise logic gate such as ANDGate has two inputs. The LookupTable device is not integrated unless specifying it in add_ops argument.

• use_fp – If it is True, all floating-point operator devices other than architecture-specific ones are integrated. The integration can be done only if an appropriate version of softfloatpy module is found.

• use_fp_riscv –

  If it is True, all floating-point operator devices specific to RISC-V are integrated. The integration can be done only if an appropriate version of softfloatpy module is found.

• add_ops – The additional operator devices.

Raises:

RuntimeError –

If no appropriate version of softfloatpy module is found.

property dsize: tuple[int, ...]

The word widths in bits.

class simuhw.alu.SIMD_FullArithmeticLogicUnit(width: int, dsize: int | Iterable[int], *, with_non_simd: bool = True, use_int: bool = True, use_fp: bool = False, use_fp_riscv: bool = False, add_ops: Iterable[Operator] = [])

Bases: GenericArithmeticLogicUnit

A SIMD full arithmetic logic unit.

This device integrates all non-SIMD and SIMD operator devices supported by SimuHW.

__init__(width: int, dsize: int | Iterable[int], *, with_non_simd: bool = True, use_int: bool = True, use_fp: bool = False, use_fp_riscv: bool = False, add_ops: Iterable[Operator] = []) → None

Creates a SIMD full arithmetic logic unit.

Parameters:

• width – The total width of words in bits.

• dsize – The selectable word width or widths in bits.

• with_non_simd – If it is True, non-SIMD operator devices are also integrated.

• use_int – If it is True, all integer operator devices other than architecture-specific ones are integrated. Every multiple-input bitwise logic gate such as ANDGate has two inputs. The LookupTable device is not integrated unless specifying it in add_ops argument.

• use_fp –

  If it is True, all floating-point operator devices other than architecture-specific ones are integrated. The integration can be done only if an appropriate version of softfloatpy module is found.

• use_fp_riscv –

  If it is True, all floating-point operator devices specific to RISC-V are integrated. The integration can be done only if an appropriate version of softfloatpy module is found.

• add_ops – The additional operator devices.

Raises:

• ValueError – If width is not divisible by any of dsize.

• RuntimeError –

  If no appropriate version of softfloatpy module is found.

property width: int

The total width of words in bits.

property dsize: tuple[int, ...]

The word widths in bits.

class simuhw.alu.ArithmeticLogicUnit74181(width: int)

Bases: BinaryOperator

An arithmetic logic unit 74181 with arbitrary bits.

This device behaves like the logic IC 74181 with no timing delay and with arbitrary bits.

Truth Tables:

[Active-Low Data]  a: first operand, b: second operand, f: result
+-----------------------+--------------+-----------------------------------------------------+
|       Selection       |     m = H    |                      m = L                          |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+
| s3  | s2  | s1  | s0  |    ci = X    |         ci = L         |           ci = H           |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+
|  L  |  L  |  L  |  L  | f =    ~a    | f =  a - 1             | f =  a                     |
|  L  |  L  |  L  |  H  | f = ~(a & b) | f = (a & b) - 1        | f =  a & b                 |
|  L  |  L  |  H  |  L  | f =  ~a | b  | f = (a & ~b) - 1       | f =  a & ~b                |
|  L  |  L  |  H  |  H  | f =     1    | f = -1                 | f =  0                     |
|  L  |  H  |  L  |  L  | f = ~(a | b) | f =  a + (a | ~b)      | f =  a + (a | ~b) + 1      |
|  L  |  H  |  L  |  H  | f =    ~b    | f = (a & b) + (a | ~b) | f = (a & b) + (a | ~b) + 1 |
|  L  |  H  |  H  |  L  | f = ~(a ^ b) | f =  a - b - 1         | f =  a - b                 |
|  L  |  H  |  H  |  H  | f =   a | ~b | f =  a | ~b            | f = (a | ~b) + 1           |
|  H  |  L  |  L  |  L  | f =  ~a & b  | f =  a + (a | b)       | f =  a + (a | b) + 1       |
|  H  |  L  |  L  |  H  | f =   a ^ b  | f =  a + b             | f =  a + b + 1             |
|  H  |  L  |  H  |  L  | f =     b    | f = (a & ~b) + (a | b) | f = (a & ~b) + (a | b) + 1 |
|  H  |  L  |  H  |  H  | f =   a | b  | f =  a | b             | f = (a | b) + 1            |
|  H  |  H  |  L  |  L  | f =     0    | f =  a + a             | f =  a + a + 1             |
|  H  |  H  |  L  |  H  | f =   a & ~b | f = (a & b) + a        | f = (a & b) + a + 1        |
|  H  |  H  |  H  |  L  | f =   a & b  | f = (a & ~b) + a       | f = (a & ~b) + a + 1       |
|  H  |  H  |  H  |  H  | f =     a    | f =  a                 | f =  a + 1                 |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+

[Active-High Data]  a: first operand, b: second operand, f: result
+-----------------------+--------------+-----------------------------------------------------+
|       Selection       |     m = H    |                      m = L                          |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+
| s3  | s2  | s1  | s0  |    ci = X    |         ci = H         |           ci = L           |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+
|  L  |  L  |  L  |  L  | f =    ~a    | f =  a                 | f =  a + 1                 |
|  L  |  L  |  L  |  H  | f = ~(a | b) | f =  a | b             | f = (a | b) + 1            |
|  L  |  L  |  H  |  L  | f =  ~a & b  | f =  a | ~b            | f = (a | ~b) + 1           |
|  L  |  L  |  H  |  H  | f =     0    | f = -1                 | f =  0                     |
|  L  |  H  |  L  |  L  | f = ~(a & b) | f =  a + (a & ~b)      | f =  a + (a & ~b) + 1      |
|  L  |  H  |  L  |  H  | f =    ~b    | f = (a | b) + (a & ~b) | f = (a | b) + (a & ~b) + 1 |
|  L  |  H  |  H  |  L  | f =   a ^ b  | f =  a - b - 1         | f =  a - b                 |
|  L  |  H  |  H  |  H  | f =   a & ~b | f = (a & ~b) - 1       | f =  a & ~b                |
|  H  |  L  |  L  |  L  | f =  ~a | b  | f =  a + (a & b)       | f =  a + (a & b) + 1       |
|  H  |  L  |  L  |  H  | f = ~(a ^ b) | f =  a + b             | f =  a + b + 1             |
|  H  |  L  |  H  |  L  | f =     b    | f = (a | ~b) + (a & b) | f = (a | ~b) + (a & b) + 1 |
|  H  |  L  |  H  |  H  | f =   a & b  | f = (a & b) - 1        | f =  a & b                 |
|  H  |  H  |  L  |  L  | f =     1    | f =  a + a             | f =  a + a + 1             |
|  H  |  H  |  L  |  H  | f =   a | ~b | f = (a | b) + a        | f = (a | b) + a + 1        |
|  H  |  H  |  H  |  L  | f =   a | b  | f = (a | ~b) + a       | f = (a | ~b) + a + 1       |
|  H  |  H  |  H  |  H  | f =     a    | f =  a - 1             | f =  a                     |
+-----+-----+-----+-----+--------------+------------------------+----------------------------+

__init__(width: int) → None

Creates an arithmetic logic unit 74181 with arbitrary bits.

Parameters:

width – The word width in bits.

property port_s: InputPort

The selection port.

The width is 4 bits.

property port_m: InputPort

The mode control port.

The width is 1 bit.

property port_ci: InputPort

The carry input port.

The width is 1 bit.

property port_co: OutputPort

The carry output port.

The width is 1 bit.

property port_po: OutputPort

The carry propagation output port.

The width is 1 bit.

property port_go: OutputPort

The carry generation output port.

The width is 1 bit.

property port_cmp: OutputPort

The comparator port.

The width is 1 bit.

reset() → None

Resets the states.

work(time: float | None) → tuple[list[InputPort], float | None]

Makes the device work.

Parameters:

time – The current time in seconds. None when starting to make the device work.

Returns:

A tuple of the list of the input ports that are to be watched receive a signal, and the next resuming time in seconds. The next resuming time can be None if resumable anytime.

class simuhw.alu.LookAheadCarryGenerator74182(ntargets: int)

Bases: Device

A look-ahead carry generator 74182 with arbitrary target slice ALUs.

This device behaves like the logic IC 74182 with no timing delay and with arbitrary target slice ALUs.

Truth Tables:

Below is the tables when ntargets is 4.

+-----------------------------------------+-------+
|                 Inputs                  |Output |
+-----+-----+-----+-----+-----+-----+-----+-------+
| g3  | g2  | g1  | g0  | p3  | p2  | p1  |   g   |
+-----+-----+-----+-----+-----+-----+-----+-------+
|  L  |  X  |  X  |  X  |  X  |  X  |  X  |   L   |
|  X  |  L  |  X  |  X  |  L  |  X  |  X  |   L   |
|  X  |  X  |  L  |  X  |  L  |  L  |  X  |   L   |
|  X  |  X  |  X  |  L  |  L  |  L  |  L  |   L   |
|         all other combinations          |   H   |
+-----------------------------------------+-------+

+-----------------------+-------+
|        Inputs         |Output |
+-----+-----+-----+-----+-------+
| p3  | p2  | p1  | p0  |   p   |
+-----+-----+-----+-----+-------+
|  L  |  L  |  L  |  L  |   L   |
| all other combinations|   H   |
+-----------------------+-------+

+-----------------+-------+
|     Inputs      |Output |
+-----+-----+-----+-------+
| g0  | p0  | ci  |  co0  |
+-----+-----+-----+-------+
|  L  |  X  |  X  |   H   |
|  X  |  L  |  H  |   H   |
| all other comb. |   L   |
+-----------------+-------+

+-----------------------------+-------+
|           Inputs            |Output |
+-----+-----+-----+-----+-----+-------+
| g1  | g0  | p1  | p0  | ci  |  co1  |
+-----+-----+-----+-----+-----+-------+
|  L  |  X  |  X  |  X  |  X  |   H   |
|  X  |  L  |  L  |  X  |  X  |   H   |
|  X  |  X  |  L  |  L  |  H  |   H   |
|   all other combinations    |   L   |
+-----------------------------+-------+

+-----------------------------------------+-------+
|                 Inputs                  |Output |
+-----+-----+-----+-----+-----+-----+-----+-------+
| g2  | g1  | g0  | p2  | p1  | p0  | ci  |  co2  |
+-----+-----+-----+-----+-----+-----+-----+-------+
|  L  |  X  |  X  |  X  |  X  |  X  |  X  |   H   |
|  X  |  L  |  X  |  L  |  X  |  X  |  X  |   H   |
|  X  |  X  |  L  |  L  |  L  |  X  |  X  |   H   |
|  X  |  X  |  X  |  L  |  L  |  L  |  H  |   H   |
|         all other combinations          |   L   |
+-----------------------------------------+-------+

__init__(ntargets: int) → None

Creates a look-ahead carry generator 74182 with arbitrary target slice ALUs.

Parameters:

ntargets – The number of the target slice ALUs.

property ntargets: int

The number of the target slice ALUs.

property port_ci: InputPort

The carry input port.

The width is 1 bit.

property ports_gi: tuple[InputPort, ...]

The carry generation input ports.

The number of the ports is ntargets. Each width is 1 bit.

property ports_pi: tuple[InputPort, ...]

The carry propagation input ports.

The number of the ports is ntargets. Each width is 1 bit.

property ports_co: tuple[OutputPort, ...]

The carry output ports.

The number of the ports is ntargets - 1. Each width is 1 bit.

property port_go: OutputPort

The carry generation output port.

The width is 1 bit.

property port_po: OutputPort

The carry propagation output port.

The width is 1 bit.

reset() → None

Resets the states.

work(time: float | None) → tuple[list[InputPort], float | None]

Makes the device work.

Parameters:

time – The current time in seconds. None when starting to make the device work.

Returns:

A tuple of the list of the input ports that are to be watched receive a signal, and the next resuming time in seconds. The next resuming time can be None if resumable anytime.